SVA在层次化验证平台中的应用  

Application of SVA in hiberarchy testbench

作　　者：李忠孝[1] 申敏[1] 

机构地区：[1]重庆邮电大学重邮信科集团股份有限公司,重庆400065

出　　处：《电子测试》2009年第5期65-69,共5页Electronic Test

摘　　要：在越来越复杂的SoC芯片验证开发中,ABV(基于断言的验证)已经成为一种先进且有效的验证方法。SVA(System Verilog断言)是一种基于描述性的验证语言,它作为System Verilog语言的一个子集已成为IEEE1800标准。本文以AMBA APB总线上的IIC总线控制器为例,简要介绍了利用VMM验证方法学来快速搭建以覆盖率为指导、约束随机化、可重用的分层验证平台。在此基础上详细阐述了在DUT的外部接口上绑定SVA断言检查器,从而在黑盒的条件下完成高效的功能验证。In the more and more complex SoC chip validate development,Assertion Based Verification become a sophisticated and efficient verification methodologies. SVA（SystemVerilog Assetions）is a based on descriptive validate language, it is a subset of SystemVerilog language that has become IEEE 1800 standard. In this paper, IIC bus controller that is connected in AMBA APB bus as an example, briefly introduce using the VMM verification methodology quickly establish a Coverage-Driven, constrained randomization, reusable layered testbeneh. Base on above,it is described how to binding SVA assertion checker in the design under test＇s external interface,so that in the black box condition achieve efficient function verification.

关 键 词：SVA nn压 ABV 断言检查器 IIC控制器 

分 类 号：TN407[电子电信—微电子学与固体电子学]