基于Verilog HDL的IEEE1394协议中CRC校验的实现  

Implementation of CRC in IEEE1394 Based on Verilog HDL

作　　者：张艳[1] 李现国[2] 

机构地区：[1]天津城市建设学院,天津300384 [2]天津工业大学,天津300160

出　　处：《现代计算机》2009年第4期97-99,共3页Modern Computer

摘　　要：CRC是IEEE1394协议中重要的错误检测和恢复机制。介绍循环冗余校验的基本原理,根据IEEE1394协议中CRC码的产生原理,分析CRC校验的具体计算过程,讨论IEEE1394协议中CRC的FPGA实现,借助EDA工具和Verilog HDL语言实现了对这种算法的仿真和验证。As an important error detection measure and resume mechanism, CRC protects over primary packets in IEEE1394. Introduces the basic principle of cyclic redundancy check and the produce principle of cyclic redundancy code in IEEE1394, and analyses the computational process of CRC, discusses the implementation of CRC in IEEE1394 based on FPGA is discussed. By the use of Verilog HDL in virtue of EDA, the CRC-32 algorithm in IEEE1394 is simulated and verified.

关 键 词：IEEE1394 CRC(循环冗余码校验) VERILOG HDL 

分 类 号：TP393.04[自动化与计算机技术—计算机应用技术]