一种电荷泵锁相环频率合成器的设计  

The Design of Charge Pump PLL Frequenc Synthesizer

作　　者：黄召军[1,2] 林武平[1,2] 李亮[1,2] 张树丹[2] 

机构地区：[1]江南大学,江苏无锡214122 [2]中国电子科技集团公司第五十八研究所,江苏无锡214035

出　　处：《微电子学与计算机》2009年第5期183-186,共4页Microelectronics & Computer

摘　　要：基于SMIC的0.25μm工艺设计了一种输出频率范围为0.32～1.6GHz的电荷泵锁相环频率合成器电路.该电路采用了一种快速鉴频鉴相器和含有双交叉耦合结构的环形振荡器,同时根据电荷泵泵电流匹配的原则改进了电荷泵电路.HSIM仿真显示,锁相环频率合成器的锁定时间为1.3μs,功耗为28mW,锁定范围为5～20MHz,最大周对周抖动仅为50ps(0.8GHz).A kind of PLL frequency synthesizer circuit is presented in this paper with the SMIC＇s 0.25μm process and its output frequency is from 0.32GHz to 1.6GHz.A fast speed PFD and ring vco with cross-coupling strecture is used in this circuit.At the same time,the charge pump circuit is improved for the principle of charge pump pump current matching.Simulations using HSIM show that the locking time of the PLL frequency synthesizer is 1.3μs,the power is 28mW,the locking rang is from 5MHz to 20MHz,and the biggest cycle to cycle jitter is only 50ps（0.8GHz）.

关 键 词：锁相环频率合成器 电荷泵 共源共栅 抖动 

分 类 号：TN4[电子电信—微电子学与固体电子学]