基于DSP和FPGA的UART系统设计  

Design of UART Based on DSP and FPGA

作　　者：李军辉[1] 李紫阳 张雪[3] 

机构地区：[1]东南大学交通学院,江苏南京210096 [2]沈阳军区某部司令部,辽宁沈阳110000 [3]东南大学仪器科学与工程学院,江苏南京210096

出　　处：《苏州科技学院学报（自然科学版）》2009年第2期55-59,共5页Journal of Suzhou University of Science and Technology （Natural Science Edition）

摘　　要：基于DSP和FPGA的异步串口UART的工作原理和软、硬件设计。采用DSP作为处理器,将UART的核心功能嵌入到PFGA内部,并利用DSP的EDMA功能完成FPGA内部FIFO和DSP内部RAM中乒乓缓冲器之间的数据传输。使用VHDL硬件描述语言对PFGA进行编程,并在Quartus II 7.2中完成了时序仿真,最后在Altera的CYCLONE系列FPGA上下载实现,验证了用FPGA实现串口通信的可行性。This paper introduces the working strategy, software and hardware designs of UART based on DSP and FPGA. In the system, DSP is used to be a processor and the core function of UART is embedded into FPGA. In addition, the ping-pong buffers are designed in the RAM of DSP and the EDMA （Enhanced Direct Memory Access） is used for transmitting the data between the FIFOs and ping-pong buffers. PFGA is programmed with VHDL hardware description language. Time series simulation is completed in Quartus II 7.2. Finally the program is loaded into the FPGA device Cyclone produced by the Altera company, and the feasibility of using FPGA to realize UART communication is demonstrated.

关 键 词：DSP FPGA 异步串行接口 先入先出数据缓存器 VHDL 

分 类 号：TP312[自动化与计算机技术—计算机软件与理论]