一种基于FPGA／SOPC的逻辑分析仪设计  

Design of Logic Analyzer Based on FPGA/SOPC

作　　者：许浩[1,2] 宋跃[1] 余炽业[1] 汪振[1,2] 

机构地区：[1]东莞理工学院,广东东莞523808 [2]华南理工大学,广东广州510640

出　　处：《仪表技术与传感器》2009年第4期115-117,共3页Instrument Technique and Sensor

基　　金：广东省工业攻关计划(2006A10102004);东莞市2006年科技计划项目(第2批序号11);东莞市科研发展专项资金项目(2005D040)

摘　　要：设计一种基于FPGA/SOPC的逻辑分析仪器,通过自定义的软核把各个外围功能部件和数字逻辑电路连结在一块FPGA中,在N ios-II软核的控制下自动实现32个通道、100 MHz采样速率、256 K存储深度的逻辑信号的采集、触发、存储及显示等功能。文中详细介绍逻辑分析仪的SOPC设计思想和实现原理,同时叙述了采样和数据存储电路以及触发核中序列触发的设计方法。实践表明,该设计方法是有效和切实可行的。In order to design a logic analyzer based on FPGA/SOPC, every peripheral functional components and main digital logic circuit were connected by customized soft core which implemented in a single FPGA to realize logic data collection, data triggering, storing and display. With 32 channels, 100 MHz sampling,256 K storage depth. The principle of realizing realize logic analyzer using SOPC and design thought were mainly introduced. A sequential trigger in the trigger core, data acquisition and memory circuit were also discussed. Practices showed that this design scheme was feasible and effective.

关 键 词：逻辑分析仪 FPGA/SOPC NIOS-II 序列触发 数据采集 

分 类 号：TP216[自动化与计算机技术—检测技术与自动化装置]