Challenges in Atomic-Scale Characterization of High-k Dielectrics and Metal Gate Electrodes for Advanced CMOS Gate Stacks  

作　　者：Xinhua Zhu Jian-min Zhu Aidong Li Zhiguo Liu Naiben Ming 

机构地区：[1]National Laboratory of Solid State Microstructures, Department of Physics, Nanjing University, Nanjing 210093, China

出　　处：《Journal of Materials Science & Technology》2009年第3期289-313,共25页材料科学技术（英文版）

基　　金：support from Natural Science Foundation of Jiangsu Province (ProjectNo. BK2007130);National Natural Science Foundation of China (Grant Nos. 10874065, 60576023 and 60636010);Ministry of Science and Technology of China (Grant No.2009CB929503);Ministry of Science and Technology of China (Grant Nos. 2009CB929503 and2009ZX02101-4);the project sponsored by the Scientific Research Foundation for the Returned Overseas Chinese Scholars, State Education Ministry;National Found for Fostering Talents of Basic Science (NFFTBS) (ProjectNo. J0630316)

摘　　要：The decreasing feature sizes in complementary metal-oxide semiconductor （CMOS） transistor technology will require the replacement of SiO2 with gate dielectrics that have a high dielectric constant （high-k） because as the SiO2 gate thickness is reduced below 1.4 nm, electron tunnelling effects and high leakage currents occur in SiO2, which present serious obstacles to future device reliability. In recent years significant progress has been made on the screening and selection of high-k gate dielectrics, understanding their physical properties, and their integration into CMOS technology. Now the family of hafnium oxide-based materials has emerged as the leading candidate for high-k gate dielectrics due to their excellent physical properties. It is also realized that the high-k oxides must be implemented in conjunction with metal gate electrodes to get sufficient potential for CMOS continue scaling. In the advanced nanoscale Si-based CMOS devices, the composition and thickness of interfacial layers in the gate stacks determine the critical performance of devices. Therefore, detailed atomic- scale understandings of the microstructures and interfacial structures built in the advanced CMOS gate stacks, are highly required. In this paper, several high-resolution electron, ion, and photon-based techniques currently used to characterize the high-k gate dielectrics and interfaces at atomic-scale, are reviewed. Particularly, we critically review the research progress on the characterization of interface behavior and structural evolution in the high-k gate dielectrics by high-resolution transmission electron microscopy （HRTEM） and the related techniques based on scanning transmission electron microscopy （STEM）, including high-angle annular dark- field （HAADF） imaging （also known as Z-contrast imaging）, electron energy-loss spectroscopy （EELS）, and energy dispersive X-ray spectroscopy （EDS）, due to that HRTEM and STEM have become essential metrology tools for characterizing the dielectric gate sThe decreasing feature sizes in complementary metal-oxide semiconductor （CMOS） transistor technology will require the replacement of SiO2 with gate dielectrics that have a high dielectric constant （high-k） because as the SiO2 gate thickness is reduced below 1.4 nm, electron tunnelling effects and high leakage currents occur in SiO2, which present serious obstacles to future device reliability. In recent years significant progress has been made on the screening and selection of high-k gate dielectrics, understanding their physical properties, and their integration into CMOS technology. Now the family of hafnium oxide-based materials has emerged as the leading candidate for high-k gate dielectrics due to their excellent physical properties. It is also realized that the high-k oxides must be implemented in conjunction with metal gate electrodes to get sufficient potential for CMOS continue scaling. In the advanced nanoscale Si-based CMOS devices, the composition and thickness of interfacial layers in the gate stacks determine the critical performance of devices. Therefore, detailed atomic- scale understandings of the microstructures and interfacial structures built in the advanced CMOS gate stacks, are highly required. In this paper, several high-resolution electron, ion, and photon-based techniques currently used to characterize the high-k gate dielectrics and interfaces at atomic-scale, are reviewed. Particularly, we critically review the research progress on the characterization of interface behavior and structural evolution in the high-k gate dielectrics by high-resolution transmission electron microscopy （HRTEM） and the related techniques based on scanning transmission electron microscopy （STEM）, including high-angle annular dark- field （HAADF） imaging （also known as Z-contrast imaging）, electron energy-loss spectroscopy （EELS）, and energy dispersive X-ray spectroscopy （EDS）, due to that HRTEM and STEM have become essential metrology tools for characterizing the dielectric gate s

关 键 词：High-k gate dielectrics Metal gate electrodes  CMOS gate stack HRTEM STEM 

分 类 号：TN912.3[电子电信—通信与信息系统] TP212[电子电信—信息与通信工程]