一种流水线A/D转换器Multi-bit级增益误差校正方法  

Gain Calibration for Multi-Bit Stages in Pipelined A/D Converter

作　　者：王妍[1] 于奇[1] 宁宁[1] 杨谟华[1] 

机构地区：[1]电子科技大学电子薄膜与集成器件国家重点实验室,成都610054

出　　处：《微电子学》2009年第3期302-305,310,共5页Microelectronics

基　　金：国防科技重点实验室基金资助课题(9140c0901030701)

摘　　要：提出了一种用于流水线A/D转换器multi-bit级增益误差校正的方法及其实现方案。该方法应用改进冗余位结构,通过在其子DAC输出端引入伪随机信号测量级间增益;利用此估计值在后台进行增益误差补偿。为了验证设计,对12位流水线ADC进行系统模拟,当首级有效精度为3位,且相对增益误差为±2%时,经校正后,INL均为0.16LSB,DNL分别为0.13LSB和0.14LSB,SFDR和SNDR分别提高35dB和16dB。分析表明,该方法能有效补偿multi-bit级增益偏大或偏小的误差,进而实现增益误差校正,且不会降低ADC转换范围和增加额外的比较器。A gain calibration method for multi-bit stages and its implementation were proposed. Using a reforma tive redundant stage, gain errors were measured by pseudo-random signals, which were injected to sub-DAC＇s output and compensated in background according to the estimated value. Simulations were performed for a 12-bit pipelined ADC. Assuming the relative gain error of the 3-bit first stage is ±2%, simulation with calibration shows an improvement of 35 dB in SFDR, 16 dB in SNDR,0. 16 LSB of INL, 0. 13 LSB and 0. 14 LSB of DNL, respectively, were achieved. Analyses showed that the proposed method calibrated positive or negative gain errors in multi-bit stage without reducing conversion range of ADC or using extra comparators.

关 键 词：A/D转换器 Multi-bit级 增益误差校正 

分 类 号：TN792[电子电信—电路与系统]