具有概率分离计算功能的二级流水线电路设计  

Design of a Two-Stage Pipelined Circuit with Probability Splitting Calculation

作　　者：杨曙辉[1] 仇玉林[2] 

机构地区：[1]北京信息科技大学光电信息与通信工程学院,北京100101 [2]中国科学院微电子研究所,北京100029

出　　处：《微电子学》2009年第3期357-361,共5页Microelectronics

基　　金：国家高技术研究发展(863)计划基金资助项目(2007AA04Z352);国家自然科学基金资助项目(60501007);北京市教委科技项目(KM200510772007);北京市属高校人才强教计划资助项目(71A0811104)

摘　　要：在通信系统的接收机中,解调器的输出通常是串行的"软比特"信息。利用模拟电路设计的信道译码器需要并行的数据,以实现后验概率译码计算。为了实现串并转换以及降低模拟译码器的复杂度和功耗,利用0.6μm CMOS工艺,为模拟译码器设计了新型的二级流水线结构的输入接口电路。在实现"软比特"信息串并转换的同时,具有概率分离计算功能。模拟结果表明,该电路比传统的设计方法降低了功耗和芯片面积,工作速度可达50MHz,整体功耗为304.8μW。In the receiver of the communication system, the output of demodulator is usually serial ＂soft-bit＂ information. For channel decoder based on analog circuits, parallel data are needed to realize a-posterior probability calculation. To realize serial-to-parallel conversion and decrease the complexity and power dissipation of the analog decoder, a novel two-stage pipelined input interface circuit for analog decoder was designed based on 0. 6μm CMOS technology. The circuit could not only realize serial-to-parallel conversion of the ＂soft-bit＂ information, but also has the probability splitting calculation function. Simulation results showed that the input circuit reduced power consumption and chip area, compared with circuit designed using conventional method. Operating at 50 MHz, the circuit had a total power dissipation of 304. 8 μW.

关 键 词：二级流水线电路 概率分离计算 模拟译码器 串并转换 

分 类 号：TN432[电子电信—微电子学与固体电子学]