基于单电子晶体管的动态全加器电路设计  

A Dynamic Full Adder Circuit Based on Single Electron Transistors

作　　者：吴刚[1] 蔡理[1] 李芹[1] 

机构地区：[1]空军工程大学理学院,西安710051

出　　处：《微电子学》2009年第3期405-409,共5页Microelectronics

基　　金：陕西省自然科学基础研究计划基金资助项目(2005F20)

摘　　要：基于单电子晶体管的I-V特性,运用CMOS动态电路的设计思想,提出了一种基于单电子晶体管的全加器动态电路,利用SPICE对设计的电路进行了仿真验证,分析了电荷分享问题。相对于静态互补逻辑电路的设计方法,基于单电子晶体管的动态逻辑电路不仅克服了单电子晶体管固有的电压增益低的缺点,而且器件数目也大幅减少。多栅SET的使用可以减少电荷分享问题对动态电路的影响。Based on the I-V characteristics of single electron transistor （SET） and the design concept of dynamic circuit, a dynamic full adder circuit was proposed using multi-gate single-electron transistors. The circuit was simulated with SPICE for verification, and the problem of charge sharing was analysed. With this dynamic logic circuit based on SET, the disadvantage of low gain, which is inherent to SET, could be overcome, and the number of devices could also be greatly reduced, compared with the static full adder. The use of multi-gate SET can alleviate the effect of charge sharing.

关 键 词：单电子晶体管 动态逻辑电路 全加器 

分 类 号：TN702[电子电信—电路与系统]