磁卡解码芯片中锁相环电路设计  

Design of PLL in Decoder

作　　者：陈亮[1] 庄华龙[1] 吴建辉[1] 

机构地区：[1]东南大学国家专用集成电路系统工程技术研究中心,南京210096

出　　处：《电子器件》2009年第2期321-323,328,共4页Chinese Journal of Electron Devices

摘　　要：为了产生一个与输入数据同步的脉冲作为磁卡解码芯片的时钟信号,设计了一种数字锁相环电路。该电路通过产生一个与输入数据周期有关的、具有特定宽度的脉冲信号来对输入信息进行处理,最终得到与输入同步的数据、时钟信号,用来控制芯片的工作;另外,该电路还具有纠错能力强,结构简单的优点。测试结果表明:加入该电路后,芯片的工作情况完全符合要求。In order to generate a pulse which is synchronized with the inputting data to be used as the clock signal of decoder, we design a digital PLL. This circuit can generate a pulse that is related to the inputting data period and has specific width to process the inputting information and finally achieves the synchronous signals of data and clock to control the working of the circuit. Besides, this circuit has the merit of strong error correction ability and simple structure. The test result shows that, after adding this circuit, the chip working meets the requirement completely.

关 键 词：磁卡解码芯片 同步信号 数字锁相环 磁条卡 

分 类 号：TN402[电子电信—微电子学与固体电子学]