卷积码的Viterbi高速译码方案  

A High-speed viterbi-decoding Scheme for Convolutional Code

作　　者：刘国锦[1] 王济生[1] 时斌[1] 朱晓舒[1] 

机构地区：[1]南京师范大学分析测试中心,江苏南京210097

出　　处：《微计算机信息》2009年第17期243-245,共3页Control & Automation

摘　　要：本文探讨了无线通信中广泛涉及的差错控制问题,介绍了卷积码的编译码原理。提出了一种卷积码编码,及其高速Viterbi译码的实现方案,对译码的各个组成部分作了分析,并在FPGA中实现了该译码方案。仿真结果表明,在纠正能力范围内,能够正确纠错并译码,且具有高速译码的优点,达到了预期的效果,该设计方案可以非常容易地应用到很多差错控制的通信系统中。This paper discusses the issue of error-control involved widely in wireless communications, and introduces the coding and endcoding principle of Convolutional Code. A scheme of encoding of Convolutional Code and its high-speed viterbi decoding is proposed, and the components of decoding are analysed, then the scheme is implemented in FPGA. The simulation result indicates that it can correct the error bits exactly within the range of capability error-correcting, and it has the advantage of high,speed decoding. Prospective effect is realized.This design scheme can be applied easily in many communication systems with error-control.

关 键 词：差错控制 卷积码 VITERBI译码 寄存器交换 

分 类 号：TN492[电子电信—微电子学与固体电子学]