FPGA动态局部可重构中基于TBUF总线宏设计  

Design of Bus Macro-based TBUF for FPGA Dynamic Reconfiguration

作　　者：赵秋桂[1] 段青亚[1] 

机构地区：[1]西安微电子技术研究所,陕西西安710054

出　　处：《现代电子技术》2009年第12期22-24,共3页Modern Electronics Technique

基　　金：星载高可靠可重构计算机体系结构技术(9140A16010407HT6902)

摘　　要：FPGA动态局部可重构技术通常将系统划分为固定模块和可重构模块,可重构模块与其他模块之间的通信都是通过使用特殊的总线宏实现的。总线宏的正确设计是实现FPGA动态局部可重构技术的关键。在研究了FPGA动态局部可重构技术中基于三态缓冲器(Tri-state Buffer,TBUF)总线宏结构的基础上,采用Xilinx ISE FPGA Editor可视化的方法实现总线宏的设计,并借助可重构硬件平台——XCV800验证板,通过设计动态可重构实验,论证总线宏设计的正确性。FPGA dynamic partial reconfiguration always divides a system into static modules and reeonfigurable modules. The communication between reconfigurable modules and the other modules should be implemented with the special bus macro. The bus macro correctly designed is the key to the implementation of FPGA dynamic partial reconfiguration. This paper researches structure of the bus macro which is based on TBUF for FPGA dynamic partial reeonfiguration,implements its design with the method of Xilinx ISE FPGA Editor,and verifies the validity of the design through the experiment of dynamic reconfiguration,with the help of reconfigurable hardware platform of XCV800.

关 键 词：FPGA动态局部可重构 总线宏 三态缓冲器 FPGA编辑器 

分 类 号：TP368.1[自动化与计算机技术—计算机系统结构]