利用FPGA延时链实现鉴相器时钟数据恢复  

A clock and data recovery method based on phase detector implemented by delay chain in FPGA

作　　者：谢明璞[1] 武杰[1] 张杰[1] 

机构地区：[1]中国科学技术大学近代物理系快电子学实验室,合肥230026

出　　处：《核技术》2009年第6期477-480,共4页Nuclear Techniques

基　　金：国家自然科学基金(10505020);中国科学技术大学研究生创新基金资助

摘　　要：为利用简单的线缆收发器,实现中等数据率的串行数据传输,提出了一种基于电荷泵式PLL的时钟数据恢复的方法。鉴相器由FPGA实现,用固定延时单元构成一条等间隔的延时链,将输入信号经过每级延时单元后的多个输出用本地的VCO时钟锁存,输入信号的沿变在延时链上所处位置的不同反应了输入信号与VCO时钟的相差。根据相差通过对电荷泵的充放电,改变VCO的控制电压,调整VCO时钟的频率及相位,使其与输入信号锁定。环路滤波器采用无源阻容滤波器,其参数由延时链以及VCO的参数计算得到。经过实验测试,在进行64 Mbps的串行数据传输时,成功恢复出时钟数据,抖动为200 ps以下。A clock and data recovery method based on charge pump PLL was developed to archive medium data rate serial digital communication with simple line transceivers. The phase detector was realized by FPGA. A delay chain was constructed by delay elements with the same fixed delay. Every output of the delay elements was latched by the VCO output clock when the input signal went through the delay chain. The latched result was used to detect the data transition, which reflected the phase difference between the input signal and the VCO output clock. The VCO control voltage was adjust by charge pump to reduce the phase difference and archive phase lock. The loop filter was a passive filter, parameters of which were calculated from parameters of the delay chain and VCO. The experimental result shows that the clock of a 64Mbps transmission was recovered with a jitter less than 200 ps.

关 键 词：时钟数据恢复 现场可编程门阵列 延时链 鉴相器 环路滤波器设计 

分 类 号：TN911.8[电子电信—通信与信息系统]