可重构单电子晶体管逻辑的设计与模拟  

Design and Simulation of a Reconfigurable Single-Electron Transistor Logic Gates

作　　者：隋兵才[1] 周海亮[1] 池雅庆[1] 方粮[1] 

机构地区：[1]国防科技大学计算机学院,湖南长沙410073

出　　处：《计算机工程与科学》2009年第7期72-76,共5页Computer Engineering & Science

摘　　要：单电子晶体管以其超小的器件尺寸和极低的功耗,被认为是最有希望代替MOS器件的技术。国内外研究人员已经提出了多种基于单电子晶体管的逻辑结构。本文在分析单电子晶体管体电压效应的基础上,首次提出了基于体电压控制的可重构单电子晶体管逻辑门(RSETLG)。SPICE的模拟结果表明,RSETLG能够以其简单的结构实现多种逻辑功能,具有很高的应用价值。Single-electronic transistors （SETs） are considered as the attractive candidates for post-COMS VLSI due to their ultra-small size and low power consumption. And many researchers have proposed many logic units based on SETs. Through the analysis of the body-voltage effect of SET, for the first time, we propose the reconfigurable SET logic gate （RSETLG） based the control of body voltage. The simulation result by SPICE shows that RSETLG can be very powerfully used to design many different logic gates because of its simple structure.

关 键 词：可重构逻辑 单电子晶体管 AND OR SPICE 

分 类 号：TN320.2[电子电信—物理电子学]