基于IEEE 802.11a的OFDM定时同步算法及FPGA实现  

FPGA Implementation of the IEEE 802.11a-Based OFDM Timing Synchronization Algorithm

作　　者：李加升[1] 尹锁柱[1] 邓茜[1] 

机构地区：[1]桂林电子科技大学信息与通信学院,广西桂林541004

出　　处：《计算机工程与科学》2009年第7期117-119,共3页Computer Engineering & Science

摘　　要：在基于IEEE802.11a标准的无线局域网的突发系统中,要求快速、精确地完成定时同步。本文分析了基于短训练序列延时自相关的粗同步算法和基于长训练序列与本地PN序列互相关的精同步算法,给出了定时同步算法具体的用FPGA实现的设计方案,采用状态机、流水线等设计方法使系统的资源和运算速度得到优化。该设计便于工程应用。In the burst IEEE 802.11a WLANs, fast and precise time synchronization is required. The coarse timing synchronization algorithm based on auto-correlation and the fine timing synchronization scheme based on cross-correlation between long sequence and local PN sequence are used in the article , and a scheme of hardware implementation based on FPGA for timing synchronization algorithms is given. It optimizes the system in the resources and the speed of operation by using the state machine and pipeline methods, and the design is convenient for engineering applications.

关 键 词：OFDM 定时同步 自相关 互相关 FPGA 

分 类 号：TP925[自动化与计算机技术]