闭环加速度计CMOS接口电路(英文)  

CMOS interface circuit for closed-loop accelerometer

作　　者：尹亮[1] 陈伟平[1,2] 刘晓为[1,2] 周治平[1] 

机构地区：[1]哈尔滨工业大学微电子技术与科学系,黑龙江哈尔滨150001 [2]哈尔滨工业大学微系统与微结构制造教育部重点实验室,黑龙江哈尔滨150001

出　　处：《光学精密工程》2009年第6期1311-1315,共5页Optics and Precision Engineering

基　　金：Supported by the National High-Tech Research and Development Program of China(863 Program)(Grant No .08AA04XK1468338)

摘　　要：采用高压18V CMOS集成电路工艺,设计了一种开关电容闭环加速度计接口电路芯片。芯片电路中包括开关电容型电荷敏感放大器,PID控制电路以及相关双采样电路。采用相关双采样技术并用大面积PMOS晶体管作前级放大器输入级来消除放大器的1/f噪声、失调电压及KT/C噪声;用高环路增益及静电力平衡技术消除后级电路的1/f噪声、电荷注入和时钟馈通。在相同电极的条件下,利用电荷检测与静电力反馈时域分离法,有效地消除了驱动馈通的影响。设计的芯片采用18V电源电压供电,闭环加速度计刻度因子为420mV/g,噪声密度为10μg/2～1/(Hz) ,芯片面积为15.2mm2。An 18 V switched-capacitor CMOS interface circuit for the closed-loop operation of a capacitive accelerometer is designed, The circuit consists of a switched-capacitor charge sense amplifier, a PID control circuit and a correlated double s,ampling circuit. The effects of the 1/f noise of the amplifier and the offset voltage of an op-amp, as well as the kT/C charge noise from the parasitic capacitor are suppressed,by taking large area PMOS transistors at the Charge Sensing Amplifier（CSA）as an input stage and using a Correlated Double Sampling （CDS） technique and the 1/f noise, charge injection and clock feedthrough effects in the back-end circuits are eliminated by the technologies of high loop gain and force feedback. Moreover, the strong driving feedthrough is avoided by separating the drive and sense operations in the time domain by using the same electrodes. The designed complete chip with an area of 15, 2 mm2 is fabricated in a 2μm two-metal and two-poly n well CMOS and operated by a single 18 V supply,which can offer a measuring sensitivity of 420 mV/g and a noise of floor of 10μg/√Hz in closed-loop.

关 键 词：接口电路 闭环加速度计 开关电容 惯性传感器 

分 类 号：TH824.4[机械工程—仪器科学与技术]