DDR控制器设计与实现  

The Design and Implementation of DDR Controller

作　　者：陈明浩[1] 王厚军[1] 戴志坚[1] 

机构地区：[1]电子科技大学测试技术及仪器研究所,成都610054

出　　处：《自动化信息》2009年第5期35-36,53,共3页Automation Information

摘　　要：DDRSDRAM具有集成度高、密度大、接口带宽高、价格便宜的特点。目前已广泛应用于PC、服务器等产品和嵌入式系统中。本文介绍了基于AlteraCycloneⅡ的DDR控制器设计和CycloneⅡ的接口以及Alter提供的控制器IP核，并讨论了根据自身应用特点简化IP核中不必要的功能，替换加密的IP核，从而实现自己的DDR控制器。该措施保证了此项目开发的速度和质量。DDR SDRAM is characterized with the advantages of high density of integration, large density, high bandwidth of interface and inexpensive price. At present, it has widely been used in PC, servers and embedded systems. Based on Altera Cyclone II the DDR controller design is introduced in this paper and it also deals with the specific structure of Cyclone II interfaces and the IP MegaCore provided by Alter. The authors simplify the unnecessary functions of IP MegaCore, replace the IP eneryption MegaCore, and thus realize own DDR controller. This measure guarantees the speed and quality of the project development.

关 键 词：DDR SDRAM IP核 CYCLONE Ⅱ 

分 类 号：TM571[电气工程—电器]