SDH设备时钟中的数字锁相环设计  

Design of Digital Phase Locked Loop Used in SDH Equipment Clock

作　　者：伍文君[1] 黄芝平[1] 章明沛[1] 刘纯武[1] 

机构地区：[1]国防科技大学机电工程与自动化学院仪器系,湖南长沙410073

出　　处：《计算机测量与控制》2009年第7期1418-1420,共3页Computer Measurement &Control

摘　　要：提出了一种新的用于实现SDH设备时钟的数字锁相环,采用时数转换器来实现数字锁相环中的鉴相器;该时数转换器的时间测量精度达到200 ps,因而极大地改进了鉴相器的鉴相精度;改进后的数字锁相环具有很好的频率稳定度和相位特性,对时钟源有很好的跟踪能力,且能实现时钟源的平滑切换,完全满足了ITU-T G.813规范要求。A novel Digital Phase Locked Loop used in SDH equipment Clock is proposed. The phase detector of the DPLL is implemented with the time--to--digital eonverter whose resolution is 200 ps. With this improvement of the phase detector＇ s resolution, the DPLL shows excellent performance. The DPLL has stable frequency output, has excellent performance to track the reference timing, and can change the reference timing smoothly. It meets the requirement given in ITU--T Recommendation G. 813.

关 键 词：SDH 数字锁相环 时数转换器 

分 类 号：TN914.332[电子电信—通信与信息系统]