适用于MPEG2标准的IDCT的新VLSI结构  

A Novel VLSI Structure of IDCT Compatible with MPEG2 Standard

作　　者：叶波[1] 俞颖[1] 章倩苓[1] 郑增钰[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海200433

出　　处：《电子学报》1998年第8期65-68,共4页Acta Electronica Sinica

摘　　要：本文提出了一种新的适用于MPEG2标准的IDCTVLSI结构，并用超高速数据语言进行了仿真．对于8点一维IDCT，只用7个变量乘常系数乘法器和10个加／减法器，且只需4个时钟就能处理完8个数据，电路规模为6000门左右，比传统方法节省40～50％．对于二维IDCT，如采用分时方式实现，处理每个8×8的块也仅需64个时钟该结构可应用于MPEG2MPHL视频解码器．A novel VLSI structure of IDCT compatible with MPEG2 is presented in this paper, and it is simulated by VHDL. For 1-D IDCT, it takes 4 clocks to process 8 point data by using only even variables multiplying constant coeffitients multipliers and 10 adders/subtracters. The design is implemented with total 6000 gates and saves 40～50% area than that of conventional design. For 2-D IDCT, if time-shared structure is used, it only takes 64 clocks to process each 8ｘ8 block. It can be used in MPEGZ MP@HL video dacoder.

关 键 词：MPEG2 IDCT VLSI 结构 图像处理 

分 类 号：TN470.3[电子电信—微电子学与固体电子学] TN919.8