基于FPGA的块浮点FFT的实现  

Implementation of block-float FFT processor with FPGA

作　　者：赵敏玲[1] 葛立敏[2] 李文辉[3] 

机构地区：[1]西安理工大学自动化与信息工程学院,陕西西安710048 [2]西北工业大学电子信息学院,陕西西安710072 [3]兰州理工大学电气工程与信息工程学院,甘肃兰州730050

出　　处：《兰州理工大学学报》2009年第4期103-106,共4页Journal of Lanzhou University of Technology

摘　　要：在分析基-2 FFT算法的基础上,提出一种用FPGA实现FFT的方法.用块浮点机制,动态扩大数据范围,在速度和精度间得到折衷;模块化设计,易于实现更多点数的FFT运算.采用Verilog语言编程实现,在Quartus II和Modelsim平台下进行逻辑综合和时序仿真,时序分析结果与Matlab计算结果相比较验证了程序的正确性.A method of implementing FFT was presented on the basis of FFT algorithm of radix 2.By using the mechanism of block-float,the range of data was dynamically increased and the advantage of speed and precision was compromised.Each component was separately designed,so that it was easy to realize FFT operation on more points.Verilog language was used in programming,and the program was synthesized and simulated in Quartus Ⅱ and Modelsim.The simulation result of Modelsim was compared with that of Matlab to verify the validity of the prograrm.

关 键 词：FFT 块浮点 FPGA 基2算法 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]