异步FIFO在USB2.0控制器中的应用  

The asynchronous FIFO design in USB2.0 controller

作　　者：许盛[1] 易浩勇[1] 

机构地区：[1]国网电力科学研究院,南京210003

出　　处：《电子测量技术》2009年第8期137-140,共4页Electronic Measurement Technology

摘　　要：本文从USB2.0控制器设计中的异步时序设计问题出发,分析了异步时钟域信号传递对ASIC设计所带来的亚稳态影响,采用异步FIFO来解决USB2.0控制器中异步跨时钟域的设计问题。设计中采用双口RAM实现异步FIFO,并且完成USB2.0控制器的RTL级设计,该设计通过了功能仿真和FPGA验证。After reviewing the problem of asynchronous timing design in USB2. 0 controller, the influence of metastability brought by signal transmission between asynchronous clock domain in ASIC design is analyzed in this paper. The asynchronous FIFO design method is used in order to solve the asynchronous clock domain design problem. An asynchronous FIFO with dual port RAM is implemented in this USB2. 0 controller design and the whole RTL design of USB2. 0 controller is completed. At last, the functional stimulation result is given and the whole controller design passed FPGA verification.

关 键 词：USB2.0 异步FIFO 亚稳态 

分 类 号：TN492[电子电信—微电子学与固体电子学]