基于SoC平台的AVS可变长解码器设计  

Design of AVS Variable Length Decoder Based on SoC Platform

作　　者：许苑丰[1] 陈泳恩[1] 刘玮[1] 王鹏[1] XU Yuan-feng, CHEN Yong-en, LIU Wei, WANG Peng （Design Center of Communication Software and ASIC,Tongji University, Shanghai 200092, China）

机构地区：[1]同济大学通信软件及专用集成电路设计中心,上海200092

出　　处：《电脑知识与技术》2009年第9期7247-7248,7253,共3页Computer Knowledge and Technology

摘　　要：AVS是我国自主制定的音视频编码技术标准。可变字长编解码是AVS标准中的一项重要技术，该文提出了一种基于SoC平台的AVS可变字长解码（VLD）设计。根据AVS变长码表的特点，重新设计合理的变长码表减少时钟消耗，采用c语言和汇编语言进行设计、模拟，并通过了SoC仿真平台验证。在164MHz工作频率下实现满足基准档次6．0级别的AVS高清视频码流的实时解码要求。AVS is the audio and video standard of China. Variable length decoding is a very important technology of AVS. This paper proposes an implementation of variable length decoder for AVS Based on SoC Platform. According to the characteristics of AVS variable length code table, the new and proper AVS variable length code table is designed to minimize the use of clock cycles. The decoder is designed, simulated based on C language and assemble language. The whole design has been verified by SoC simulation platform. Its maximal working frequency is around 164MHz and could fulfill the performance requirement of real-time AVS JiZhun profile 6.0 level decoding.

关 键 词：AVS SOC 解码器 变长解码 

分 类 号：TP311[自动化与计算机技术—计算机软件与理论;自动化与计算机技术—计算机科学与技术]