AVS视频解码中帧内预测模块的硬件化设计及SoPC验证  

Hardware design of intra-prediction for AVS video decoder & SoPC verification

作　　者：刘家良[1] 任怀鲁[1] 陈新华[1] 

机构地区：[1]山东科技大学信息科学与工程学院,山东青岛266510

出　　处：《电子技术应用》2009年第10期18-21,共4页Application of Electronic Technique

基　　金：青岛市科技计划项目(07-2-3-1-jch)

摘　　要：论述了适用于AVS解码器的帧内预测模块硬件化设计,提出了一种关键路径更短、占用资源更少的可重构运算单元(PE),利于流水线设计,可以提高运行频率。在参考样本管理方案中采用了一种环形RAM预加载方案,可以有效地提高预测速度。通过在Cyclone Ⅱ FPGA上进行测试,证明该帧内预测模块可正常工作在100 MHz频率下,解码速度提高了19.4%。This paper mainly presents the hardware design of intra-prediction for AVS video decoder. The design brings up a reusable PE whose critial path is shorter and can economize the hardware resource.This PE contributes to pipeline design and inproves the runing frequency. What is more, we adopt a kind of ring-RAM pred-load method to accelerate the intra-prediction. By being tested on the Cyclone Ⅱ FPGA, the intra-predietion module is proved to work well with 100 MHz, and the decoding speed is increased by 19.4%.

关 键 词：帧内预测 AVS视频编码标准 硬件加速 SOPC 

分 类 号：TN919[电子电信—通信与信息系统]