嵌入式组合导航系统中高速通信链的实现  

Implementation of High-Speed Communication Chain for Embedded Integrated Navigation System

作　　者：张国龙[1] 徐晓苏[1] 

机构地区：[1]东南大学仪器科学与工程学院,江苏南京210096

出　　处：《华南理工大学学报（自然科学版）》2009年第9期77-81,共5页Journal of South China University of Technology(Natural Science Edition)

基　　金：国防"973"项目(973-61334);"十一五"总装备部预研项目(51309060402;51309020503);国家自然科学基金资助项目(50575042);教育部高等学校博士点专项科研基金资助项目(20050286026);原国防科工委基础科研项目(C1420080224)

摘　　要：为满足系统小型化、低功耗、低成本、高精度等要求,在基于数字信号处理器(DSP)的嵌入式组合导航系统中,使用一片现场可编程门阵列(FPGA)芯片完成系统各单元间的逻辑控制、多通道异步收发器(UART)的扩展及其收/发双缓冲先进先出(FIFO)存储器的设计.同时,为了减少系统完成数据传输任务时CPU的额外开销,在DSP内部随机存取存储器(RAM)中设计了乒乓缓存区,并利用TMS320C6713的增强型直接内存存取(EDMA)功能完成FPGA中UART缓冲FIFO和DSP内部RAM中乒乓缓存区之间的数据传输.试验结果证明,此方案可以在CPU执行导航算法的同时,由EDMA控制多通道UART在460.8 kb/s波特率下稳定地工作,实现了DSP与外围设备之间高速通信链的设计,使得CPU更专注于导航计算.In order to meet the requirements of miniaturization,low power consumption,low cost and high precision of the embedded integrated navigation system based on the digital signal processor（DSP）,single field programmable gate array（FPGA） chip was used to control each logic module,expand the multi-channel universal asynchronous receiver transmitter（UART） and design double first-in-first-out（FIFO） memories for the data buffering of UART.In addition,for the purpose of reducing the additional CPU overhead for transmission, a Ping-Pong Buffer storage was designed in the random access memory （RAM） of DSP, and the enhanced direct memory access （EDMA） provided by TMS320C6713 was used to transmit data between the FIFO of UART in FPGA and the Ping-Pong Buffer storage. Test results indicate that the proposed scheme makes the multi-channel UART steadily operate at 460. 8 kb/s with the control of EDMA when CPU executes navigation algorithms at the same time. Thus, a high-speed communication chain between DPS and peripheral equipment is successfully implemented and CPU can be devoted further to navigation algorithms.

关 键 词：全球定位系统 惯性导航系统 数字信号处理器 现场可编程门阵列 串行通信 增强型直接内存存取 

分 类 号：V249.328[航空宇航科学与技术—飞行器设计]