基于TSDPLL的时钟漂移补偿算法容错研究  

Fault tolerance for timestamp DPLL in clock drifting compensation

作　　者：全渝娟[1,2] 刘桂雄[2] 罗三川[1] 刘波[2] 

机构地区：[1]暨南大学信息科学技术学院计算中心,广州510632 [2]华南理工大学机械与汽车工程学院,广州510640

出　　处：《计算机应用研究》2009年第11期4237-4239,4247,共4页Application Research of Computers

基　　金：广东省自然科学基金资助项目(7000815);广东省科技计划资助项目(2008B010200012;2006B12401003)

摘　　要：提出集成TSDPLL对系统节点本地时钟计时频率漂移进行有效补偿的时钟同步方法,大大提高了应用网络时间同步技术(如NTP、PTP等)的同步精度。为确保TSDPLL能在网络出现拥塞的情况下仍然正常工作,通过分析收敛函数基本特征,提出基于收敛函数的容错方案。仿真实验结果表明,该方案算法简单、容错效果明显,是基于DPLL时钟漂移补偿算法不可或缺的关键组成部分。The frequeney of a timing pulse would be compensated effectively for the local clock in a node of a distributed system within an Ethernet by the use of digital phase lock loop （DPLL） based on timestamps. Thus, much higher precision clock synchronization would be realized in a distributed system that the local clock of each nodes only equipped with a common crystal oscillate, even if adopting a common network time protocol as NTP. Ensuring the DPLL going to work when a serious congestion occurring in network, this paper presented a fault tolerance method, which was based on convergence function. The emulation results prove that the method is simple in computing and effective in fault tolerance, and the method is the key of the DPLL in clock drifting compensation.

关 键 词：时钟同步 漂移补偿 数字锁相环 时间戳 

分 类 号：TP393[自动化与计算机技术—计算机应用技术]