一种基于标准逻辑单元的GALS异步封装电路  

An asynchronous GALS wrapper based on standard logic cell

作　　者：周端[1] 朱樟明[2] 杨银堂[2] 史明华[1] 梁政 

机构地区：[1]西安电子科技大学计算机学院,陕西西安710071 [2]西安电子科技大学微电子研究所,陕西西安710071 [3]芬兰Turku计算机科学研究中心,芬兰turkufin20520

出　　处：《电路与系统学报》2009年第5期112-116,共5页Journal of Circuits and Systems

基　　金：国家自然科学基金资助项目(60725415;60676009)

摘　　要：基于点对点GALS模型,给出了异步封装电路的信号状态转换图(STG),基于Petrify设计了一种基于标准逻辑单元的GALS异步封装电路,包括同步/异步接口电路、具有分频及暂停功能的局部时钟等设计。由于所设计的异步封装电路具有不存在延时器件、没有使用特殊的异步逻辑单元等特点,所以论文基于两个同步计数器实现了GALS点对点模型进行仿真和FPGA验证,结果显示了整个异步封装及其GALS系统性能的正确性。Based on the point to point GALS model, the signal transition graph of the asynchronous wrapper is presented. A novel asynchronous wrapper for GALS systems is presented in Petrify based on the standard logic cell. The synchronous and asynchronous interface circuits, local clock circuits with frequency dividing and pause function are included in the wrapper. Because the wrapper does not include delay device and special asynchronous elements, the GALS system with the asynchronous wrapper can be verified directly in FPGA based on two synchronous counters. The simulating and verifying results for point to point GALS model show that the asynchronous GALS wrapper can operate accurately.

关 键 词：全局异步局部同步 异步封装 信号转换 标准逻辑单元 FPGA 

分 类 号：TN402[电子电信—微电子学与固体电子学]