基于Verilog-HDL的RISC/DSP微处理器IP核的设计  

Design of a RISC/DSP Microprocessor IP Core Based on Verilog-HDL

作　　者：陈芙蓉[1] 张向文[1] 曹梅双[1] 

机构地区：[1]桂林电子科技大学计算机与控制学院,广西桂林541004

出　　处：《微电子学与计算机》2009年第11期70-73,共4页Microelectronics & Computer

基　　金：国家自然科学基金项目(60804059);广西自然科学基金项目(0640172)

摘　　要：设计了一种新的既能用作通用微处理器又能用于32位定点DSP运算的RISC/DSP架构.DSP操作与ALU运算共享寄存器组,并行执行.为了提高该处理器的性能又不增加硬件复杂性,运用了可变长度的指令来提高代码密度,四级流水线提高程序执行效率,有限状态机来快速响应中断/例外.所有的模块都是基于Verilog-HDL语言,经过EDA工具的综合分析后给出了整机的RTL视图和功能仿真波形图.A new 32 bits reduced instruction set computer/digital signal processor （RISC/DSP） architecture which can be used as a general purpose microprocessor and a 32-b fixed-point DSP is presented. The integrated DSP unit operates in parallel to an arithmetic logic unit（ALU） on the same register set. The performance of this microprocessor is improved with reduced complexity. The concepts of variable instruction length for high code density, four-stage pipeline for easy programming and finite state machine for fast interrupt/exception behavior are described. All models are programmed by verilog-HDL. The RTL structure and part of functional simulation pictures are given after the EDA software＇s synthesis ＆ analysis.

关 键 词：RISC DSP 微处理器 有限状态机 RTL 

分 类 号：TP202[自动化与计算机技术—检测技术与自动化装置]