集成电路关键面积研究方法的发展与挑战  

Development of Critical Area Research Method for Integrated Circuits and Its Challenges

作　　者：张国霞[1] 马佩军[1] 张旭[1] 郝跃[1] 

机构地区：[1]西安电子科技大学微电子学院,西安710071

出　　处：《微电子学》2009年第5期704-709,共6页Microelectronics

基　　金：国家自然科学基金资助项目(60506020);陕西省自然科学基础研究项目(SJ08-ZT13)

摘　　要：关键面积研究方法是集成电路可制造性(DFM)领域的重要研究内容。对主流关键面积研究方法进行了综述与分析,讨论了Monte Carlo方法、多边形算子方法、Voronoi图方法的优缺点;对亚波长光刻阶段关键面积研究面临的挑战进行了分析与探讨。Critical area research method is one of the most important research subjects of design for manufacturability （DFM）. The mainstream critical area algorithms were summarized and analyzed. Advantages and limitations in Monte Carlo method, polygon operator method and Voronoi diagram were discussed. In addition, challenges to critical area research for deep submicron ICs using new lithography technology were analyzed and discussed in particular.

关 键 词：集成电路 关键面积 关键面积提取 深亚微米光刻 

分 类 号：TN401[电子电信—微电子学与固体电子学]