高效AVS环路滤波器结构设计  

Efficient architecture design for AVS de-blocking loop filter

作　　者：刘荣科[1] 于澎[1] 

机构地区：[1]北京航空航天大学电子信息工程学院,北京100191

出　　处：《北京航空航天大学学报》2009年第10期1237-1240,共4页Journal of Beijing University of Aeronautics and Astronautics

摘　　要：为满足AVS高清视频实时解码要求,提高环路滤波处理速度,提出了一种高效的AVS去块效应环路滤波的实用结构.将8×8块进一步分割为4×4块进行滤波运算.通过优化滤波顺序,将需要滤波的4×4块边界尽量集中,在读写数据的同时进行滤波操作,提高流水处理的效率和数据的利用率,从而有效地减少了滤波处理总的时钟数.实验结果显示,处理一个宏块只需要196个周期,相对于目前AVS环路滤波设计,速度提高50%.在100MHz工作频率下,能够支持AVS高清视频的实时解码滤波处理.In order to meet the requirements in the real time decoding of high definition（HD） video, an efficient very large-scale integration（VLSI） architecture proper for de-blocking loop filter in audio video coding standard（AVS） was presented. The 8 ×8 blocks were divided into 4 x 4 blocks for filtering operations. After centralized process of 4 × 4 block boundaries, data and filtering operations were performed at the same time by improving filtering order. This architecture can increase the efficiency of pipelining and operating data in the SRAM, thereby highly reducing the total clock cycles of filtering process. Experiment results show that only 196 clock cycles are needed to finish filtering a macro-block for de-blocking filter in AVS. The processing speed increases by 50%. When the maximum frequency is 100 MHz, the real time decoding of HD video can be achieved in this architecture.

关 键 词：视频信号处理 去块效应滤波 实时解码 高清视频 超大规模集成电路 

分 类 号：TP302.1[自动化与计算机技术—计算机系统结构]