6加数并行加法器及扩展接口的研究  

Research on a Parallel Adder with 6 Binary Addends and Its Interface

作　　者：刘杰[1] 易茂祥[2] 

机构地区：[1]阜阳师范学院物理与电子科学学院,安徽阜阳236041 [2]合肥工业大学应用物理系,安徽合肥230009

出　　处：《微电子学与计算机》2009年第12期27-30,共4页Microelectronics & Computer

基　　金：安徽省高校省级自然科学研究资金项目(2006KJ042B)

摘　　要：提出了一种6个加数的并行加法器及其接口扩展的研究方案.论述了所提新型加法器的工作原理和过程,同时描述了接口扩充思想.最后,采用MAX+PLUSⅡ对设计电路进行了模拟验证.实验结果说明了所提加法器的设计合理性,也证明了该加法器对6个加数的计算比采用串行累加更快.A parallel adder with 6 binary addends and its interface are proposed. Working principle and process of the novel adder are discussed, and its interface extension is described. Finally, MAX ＋ PLUS II is exploited to simulate and validate the proposed adder. Experimental results indicate that the proposed design scheme is not only reasonable, but also can faster calculate 6 binary addends than a carry look-ahead adder using the serial adding scheme.

关 键 词：算术逻辑运算单元 加法器 超前进位加法器 

分 类 号：TP342.21[自动化与计算机技术—计算机系统结构]