串行通信系统接口模块的设计与优化  

A Optimal design of Serial communication system interface module

作　　者：周中华[1] 侯立刚[1] 贺明[1] 吴武臣[1] 

机构地区：[1]北京工业大学集成电路与系统实验室,北京100124

出　　处：《中国集成电路》2009年第12期29-33,共5页China lntegrated Circuit

摘　　要：串行通信系统以硬件资源简单、抗干扰强、易于实现等特点在数据通信及控制系统中得到了广泛的运用。本文以FPGA为实现平台,基于UART16550通信协议及工作原理完成高性能串行通信系统接口模块的完整功能设计与优化。采用三段式状态机设计方法和EDA优化、电路优化等优化手段完成设计及优化。优化后的设计系统时钟频率最高达到166MHz,功耗降低了63.9%,达到0.147W,且给出了典型波特率115200下的板级测试数据和Matlab分析结果。实验结果证明功能正确且稳定可靠。Serial communication system has been widely used in data communications and control systems because of less hardware resources, anti-jamming ability, and easy to implement features. An FPGA-based high performance Serial communication system interface module which includes full functions of UART16550 is designed and optimized based on the communication protocol and working principles in this paper. Various technologies are adopted during the design and optimization procedure, such as EDA optimization, circuit optiinization, and so on. The frequency of the optimized design is up to 160 MHz, and the power is reduced to 0.147 W by 63.9%. The test data at typical baud-rate of 115200 and the analyzed result by using Matlab are presented. The test results indicate that the optimized design can be communicated correctly and steadily.

关 键 词：串行通信 现场可编程门阵列 时序优化 静态时序分析 Matlab分析 

分 类 号：TN914[电子电信—通信与信息系统]