800Mbps准循环LDPC码编码器的FPGA实现  

An 800Mbps Quasi-Cyclic LDPC Encoder Implementation with FPGA

作　　者：张仲明[1] 许拔[1] 杨军[1] 张尔扬[1] 

机构地区：[1]国防科技大学电子科学与工程学院,湖南长沙410073

出　　处：《信号处理》2009年第12期1937-1940,共4页Journal of Signal Processing

摘　　要：本文提出了一种准循环低密度奇偶校验码的低复杂度高速编码器结构。通过利用循环矩阵的结构特性,增加少量的硬件开销就可以提高编码器的并行度,得到一种基于并行SRAA结构的编码算法,提高了编码器的吞吐量。这种编码方法的主要优点是复杂度较低,且编码延时小。在Xilinx Virtex 4 FPGA上实现了(8176,7154)有限几何LDPC码的编码器,吞吐量达到800Mbps。This paper presents a low-complexity, high-speed encoder architecture for QC-LDPC code. In the design, the character of circulant matrix is employed to increase the parallelism of encoder through the introduction of small hardware overhead. A type of encoding circuits using parallel architectures of shift-register-adder-accumulator（SRAA） is designed to increase the throughput of encoders. A major feature of the high speed encoding is that it has an extremely low latency and low complexity. Results show that the proposed encoder for an （8176,7154） Finite Geometries LDPC code can achieve an information encoding throughput over 800 Mbps on Xilinx Virtex 4 FPGA.

关 键 词：循环矩阵 准循环低密度奇偶校验码 快速编码 

分 类 号：TN911.22[电子电信—通信与信息系统]