基于Verilog HDL的多功能车辆总线编码器设计  

Design of encoder for MVB network based on verilog HDL

作　　者：邝艳菊[1] 黄采伦[1] 周华[1] 张剑[2] 王靖[2] 陈特放[2] 黄晓煌[1] 

机构地区：[1]湖南科技大学机械设备健康维护省重点实验室,湘潭411201 [2]中南大学信息科学与工程学院,长沙410075

出　　处：《铁路计算机应用》2009年第10期8-11,共4页Railway Computer Application

基　　金：863计划项目(2006AA11Z230);国家自然科学基金资助项目(60674003);湖南科技大学研究生创新基金资助项目

摘　　要：讨论多功能车辆总线MVB以及目前国内外MVB网络产品的开发情况,阐述IP核的基本特征及其在SOPC设计中的重要性。在此基础上,设计MVB Encoder模块的总体方案,采用Verilog硬件描述语言在QUARTUS II6.0上实现其IP核的设计,通过Modelsim SE6.2b仿真平台对MVB主帧进行仿真验证。仿真结果表明设计的正确性,可为MVB网络产品的开发提供一种有效的实现方法。The Multifunction Vehicle Bus was discussed in this paper. Moreover, the development of the current situation of the MVB network products both at home and abroad was expounded. It was also expounded the basic characteristics of IP core and the importance of it in SOPC designs. With this foundation, a MVB encoder module＇s complete solution was presented and the MVB encoder IP core was designed, in which Verilog hardware description language was applied for its programming on a QUARTUS II 6.0 platform. Finally, the MVB main frame was simulated on a Modelsim SE 6.2h platform and the Simulated results verified the correctness of the design, which provided an effective solution for MVB networt products.

关 键 词：多功能车辆总线 编码器 IP核 硬件描述语言 

分 类 号：U28[交通运输工程—交通信息工程及控制]