A low power high gain UWB LNA in 0.18-μm CMOS  

作　　者：蔡力 傅忠谦 黄鲁 

机构地区：[1]Department of Electronic Science and Technology,University of Science and Technology of China

出　　处：《Journal of Semiconductors》2009年第11期94-98,共5页半导体学报（英文版）

基　　金：Project supported by the National High Technology Research and Development Program of China (No.2007AA01Z2b2)

摘　　要：A low power high gain differential UWB low noise amplifier （LNA） operating at 3-5 GHz is presented. A common gate input stage is used for wideband input matching; capacitor cross coupling （CCC） and current reuse techniques are combined to achieve high gain under low power consumption. The prototypes fabricated in 0.18-μm CMOS achieve a peak power gain of 17.5 dB with a -3 dB bandwidth of 2.8-5 GHz, a measured minimum noise figure （NF） of 3.35 dB and -12.6 dBm input-referred compression point at 5 GHz, while drawing 4,4 mA from a 1.8 V supply. The peak power gain is 14 dB under a 4.5 mW power consumption （3 mA from a 1.5 V supply）. The proposed differential LNA occupies an area of 1,01 mm^2 including test pads.A low power high gain differential UWB low noise amplifier （LNA） operating at 3-5 GHz is presented. A common gate input stage is used for wideband input matching; capacitor cross coupling （CCC） and current reuse techniques are combined to achieve high gain under low power consumption. The prototypes fabricated in 0.18-μm CMOS achieve a peak power gain of 17.5 dB with a -3 dB bandwidth of 2.8-5 GHz, a measured minimum noise figure （NF） of 3.35 dB and -12.6 dBm input-referred compression point at 5 GHz, while drawing 4,4 mA from a 1.8 V supply. The peak power gain is 14 dB under a 4.5 mW power consumption （3 mA from a 1.5 V supply）. The proposed differential LNA occupies an area of 1,01 mm^2 including test pads.

关 键 词：UWB LNA high gain low power 

分 类 号：TN722.3[电子电信—电路与系统]