利用FPGA实现HDB3编解码功能  

Utilize FPGA to achieve HDB3 coder and decoder function

作　　者：朱勤为[1] 唐宁[1] 赵明剑[1] 

机构地区：[1]桂林电子科技大学信息与通信学院,广西桂林541004

出　　处：《电子设计工程》2009年第12期76-79,共4页Electronic Design Engineering

摘　　要：HDB3(三阶高密度双极性)码具有无直流分量、低频成分少、连零个数不超过3个、便于提取时钟信号等特点。通过对HDB3编解码原理进行分析和研究,提出一种基于FPGA的HDB3编解码实现方法,给出Verilog HDL语言的实现方法和仿真波形,完成硬件电路的设计和测试,采用该方法设计的HDB3编解码器已应用于相关实验设备中。The HDB3 code（High Density Bipolar of order 3 code）has the features of no DC component,little low frequency component and less than three zero string, making the extraction of clock signal is more accessible.Through analyzing the principle of HDB3 coding and decoding,a new coding and decoding method based on FPGA is proposed.All the modules are programmed and simulated by Verilog HDL.And the hardware circuit is designed and tested.The HDB3 coder and decoder have been applied to related experimental equipment.

关 键 词：HDB3编码 HDB3解码 FPGA VERILOG HDL 

分 类 号：TN911.2[电子电信—通信与信息系统]