AES算法中S-box和列混合单元的优化及FPGA实现  

Optimization of S-box and MixColumn Blocks in AES Encryption Algorithm and FPGA Implementation

作　　者：夏克维[1] 李冰[1] 

机构地区：[1]东南大学集成电路学院,江苏南京210096

出　　处：《现代电子技术》2009年第24期11-14,共4页Modern Electronics Technique

摘　　要：由于AES算法的硬件实现较为复杂,在此提出一种优化算法中S-box和列混合单元的方法。其中S-box通过组合和有限域映射的方法进行优化,列混合单元使用算式重组的方法进行优化。这些优化设计通过组合逻辑实现,经过仿真并在Xilinx Spartan 3系列FPGA上进行综合验证,可以将结构简化,使AES电路面积得到优化,明显节约硬件资源。AES encryption algorithm is an advanced encryption algorithm. Because the structure of it is complex,an optimization of the algorithm is presented. The implementation of S- box and MixColumn blocks in the AES encryption is optimized by the combinational logic method. The circuit design is successfully synthesized in the Xilinx Spartan 3 FPGA device and the area of AES circuit is finely optimized.

关 键 词：AES算法 S-BOX 列混合 结构优化 FPGA实现 

分 类 号：TN710[电子电信—电路与系统]