VHDL描述的直接数字信号合成器的设计  

Design of Digital Signal Synthesizer Base on VHDL

作　　者：王鹏[1] 孙加存[1] 

机构地区：[1]苏州市职业大学电子信息工程系,江苏苏州215104

出　　处：《苏州市职业大学学报》2009年第4期15-18,共4页Journal of Suzhou Vocational University

摘　　要：介绍了基于VHDL语言描述的直接数字信号合成器的研制.该设计采用DDS的原理,通过VHDL语言进行硬件电路的描述,插入分频电路、相位累加电路可以很好地实现高频、低频信号的产生.通过软件仿真与硬件测试,效果理想,具有一定的实用价值.It introduced the design of Direct Digital Synthesizer based on VHDL. The design described the hardware circuit through VHDL and adopts the principle of DDS. The frequency division circuit and the phase addition circuit were inserted. The effect through software emulator and hardware testing is perfect and the design has some practical value.

关 键 词：VHDL DDS 相位累加 分频 

分 类 号：TP18[自动化与计算机技术—控制理论与控制工程]