一种新型CMOS集成降压源IP模块的设计  

Design of a New CMOS Integrated Drop-Out Voltage-Regulator IP Block

作　　者：谢芳[1] 戴庆元[1] 

机构地区：[1]上海交通大学微米/纳米加工技术国家重点实验室,薄膜与微细技术教育部重点实验室,上海200240

出　　处：《电子器件》2009年第6期1027-1030,共4页Chinese Journal of Electron Devices

摘　　要：目前很多热插拔接口芯片,采用低电压短沟道工艺,从5 V电压得到3.3 V和1.2 V电压的稳压器就成为芯片的一部分。稳压器主要由带隙基准(BGR)、缓冲器、局部电压镜像和全局电流镜像组成。利用Spectre对降压源仿真表明:不带负载功耗280μA;3.3 V输出偏差在3.5%内,负载电阻下限200Ω;1.2 V输出偏差在4%以内,负载电阻下限73.5Ω。该减压源IP模块采用0.13μm CMOS工艺实现,具有实用性。Now a lot of hot pluggable IO interface chips are implemented on low-voltage short -channel IC process. An integrated drop-out voltage-regulator IP block, providing a solution of obtaining 3.3 V and 1.2 V from 5 V voltage source is a necessary part in the chips. The block is composed of Band-Gap-Reference（BGR）, buffers, local voltage mirror and global current mirror. Simulation using Spectre indicates that the power dissipation is 280 μA without resistivity load; the 3.3 V output deviation is controlled within 3.5% and lower-limited load resistance is 200 12;the 1.2 V output deviation is controlled within 4% and lower-limited load resistance is 73. 5 ΩThe design of the block is implemented on the 0. 13μm CMOS process,having practical value.

关 键 词：降压源 带隙基准 低功耗 共源输出 

分 类 号：TN432[电子电信—微电子学与固体电子学]