基于VHDL的一种低功耗新型全数字锁相环设计  

A New Low Power All-Digital PLL Design Based on VHDL

作　　者：余婷[1] 陈杰[1] 甘明刚[1] 

机构地区：[1]北京理工大学,北京100081

出　　处：《微计算机信息》2009年第35期201-202,208,共3页Control & Automation

基　　金：基金申请人:陈杰;基金颁发部门:北京市教育委员会

摘　　要：为了改善数字通信系统的同步性能,对全数字锁相环电路进行了研究。用VHDL语言设计了一种新型的超前—滞后型数字鉴相器,并构建了包含该鉴相器的全数字锁相环(DPLL),用来实现基带信号处理中的码跟踪功能。设计了双边沿触发计数器,并利用电路的冗余特性,降低了系统的功耗。提供了锁相环的仿真结果,并在Altera公司的EP2C20系列FPGA上进行了验证。分析锁相环的性能,结果表明,该锁相环完全能够满足跟踪环路的要求。In order to improve the synchronizing performance of the digital communicating system, an All-Digital PLL circuit is considered.A new lead-lag digital phase detector is designed and a All-Digital PLL which contains the phase detector is instructed, to achieve the code tracking function, which is a part of the base band signal process. A double edge triggered counter is designed, and the redundancy attribute of the circuit is utilized to decrease the power consumption of the system. The realistic result of PLL is afforded, and a check on Ahera＇s FPGA with series of EP2CEO is made. The performance of the PLL is analyzed, and the result manifests that the PLL can totally satisfy the demand of the tracking loop.

关 键 词：超前—滞后型鉴相器 全数字锁相环 双边沿触发计数器 冗余特性 

分 类 号：TN813.5[电子电信—信息与通信工程]