5加数并行加法器及其进位接口  

Parallel Adder with Five Addend and Its Carry Interface

作　　者：刘杰[1] 易茂祥[2] 

机构地区：[1]阜阳师范学院物理与电子科学学院,阜阳236041 [2]合肥工业大学应用物理系,合肥230009

出　　处：《计算机工程》2010年第1期251-252,259,共3页Computer Engineering

基　　金：安徽省高校省级自然科学研究基金资助项目(2006KJ042B)

摘　　要：传统加法器在处理多操作数累加时,必须进行多次循环相加操作。针对该问题设计5操作数并行加法器及其高速进位接口。电路采用多操作数并行本位相加和底层进位级联传递的方式,在一定程度上实现多操作数间的并行操作,减少相加次数。模拟结果验证了该加法器的设计合理性,证明其能缩短累加时间、提高运算效率。Traditional adder must do several times of cyclic addition operation in processing of multi-operand accumlation. Aiming at this problem, this paper designs a five addend parallel adder and its high speed carry interface. Because the circuit uses parallel own department addition of multi-operands and bottom layer carry cascade connection transmission mode, the parallel operation between multi-operands is realized and addition times are reduced. Simulation results verify the design reasonability of the adder and prove that it can shorten addition time, enhance operation efficiency.

关 键 词：加法器 超前进位加法器 进位接口 

分 类 号：TP342.21[自动化与计算机技术—计算机系统结构]