层次总线型多核SoC结构系统级模拟  

System level simulation of multi-processor SoC architecture based on hierarchical bus

作　　者：翁启源[1] 杨洪斌[1] 吴悦[1] 

机构地区：[1]上海大学计算机工程与科学学院,上海200072

出　　处：《计算机工程与设计》2009年第23期5355-5357,5368,共4页Computer Engineering and Design

基　　金：上海市重点学科建设基金项目(J50103)

摘　　要：随着半导体工艺技术的发展,在SoC中实现多个处理器内核成为可能。提出一种同构的层次总线型多核SoC芯片的结构,建立了这种结构系统级模型。基于模型实现了单程序多数据(SPMD)并行程序,以不同数目处理器核数仿真执行了并行程序,得到了比较好的性能加速比,充分体现了这种层次总线型多核SoC结构的可行性和性能的优越性。With the development of semiconductor technology, integrating several processor cores into a single a SoC（system on a chip） becomes possible.A kind of homogeneous SoC architecture based on hierarchical bus is proposed.A system level model is constructed and SPMD（single program multi-data） program is implemented based on the system level model.The SPMD program is run on the model with different number of the virtual processors.Finally, a good performance acceleration is obtained which fully demonstrated the feasibility and good performance of the multi-processor SoC based on hierarchical bus.

关 键 词：多核系统芯片(MPSoC) 层次总线 指令集模拟器 仿真验证 单程序多数据 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]