基于改进型Q矩阵LDPC编码的硬件实现  

Hardware implementation of LDPC coding based on an improved Q matrix

作　　者：诸叶[1] 张福洪[1] 方洪灿[1] 

机构地区：[1]杭州电子科技大学通信工程学院,浙江杭州310018

出　　处：《电子技术应用》2010年第1期57-59,63,共4页Application of Electronic Technique

摘　　要：在DVB-S2中使用LDPC码,设计了一种准规则Q矩阵LDPC码编码器。其编码复杂度与信息位的长度成正比,有效降低了编码复杂度和设计难度。根据具体实现要求,在QuartusII平台上用FPGA实现了可变码率及码长的编码器。结果证明其硬件资源占用很少,实现比较简单。A quasi-regular LDPC codes encoder based on Q-matrix is designed and implemented.The encoder is devised on the parity-check matrix of the codes directly,and its complexity is proportional to the length of information bits,which brings the advantage of low difficulty and complexity in hardware implementation. The encoder of variable bit rate, code length is realized with FPGA on QuartuslI. Its compilation report shows that it employs little logic resource and can be realized simply.

关 键 词：LDPC码 编码器 Q矩阵 

分 类 号：TN911.22[电子电信—通信与信息系统]