语音增强算法的FPGA实现  

Implementation of Speech Enhancement Algorithm on FPGA

作　　者：叶利剑[1] 黄松华[1] 王尧[1] 邱小军[2] 

机构地区：[1]AAC声学科技有限公司南京研发中心,江苏南京210009 [2]南京大学声学研究所,江苏南京210093

出　　处：《电声技术》2010年第1期67-70,共4页Audio Engineering

摘　　要：介绍了语音增强谱减算法的原理,设计并实现了基于FreeDev公司Altera CycloneII开发板的FPGA语音增强谱减算法片上实时系统。系统使用Altera提供的SOPC Builder及IP核进行硬件系统设计,在Nios II IDE开发环境下编写软件工程。实验结果表明,采用FPGA实现语音增强算法系统是有效的。The principle of a spectral subtraction speech enhancement algorithm is presented. The realtime system on chip speech enhancement system is designed and implemented using FreeDev Audio FPGA development board of Altera Cyclone Ⅱ FPGA. The hardware design is based on the SOPC Builder and IP cores, and the software is compiled on the Nios Ⅱ IDE. Experimental result indicates that it is feasible to implement the speech enhancement system implemented on FPGA. enhancement

关 键 词：FPGA NIOSII FFTIP核 语音增强 

分 类 号：TB52[理学—物理]