基于FPGA的双CPU容错控制器设计  

Design of Dual CPU Fault-tolerant Controller Based on FPGA

作　　者：李登静[1] 范守文[1] 

机构地区：[1]电子科技大学机械电子工程学院,成都610054

出　　处：《计算机工程》2010年第2期238-240,共3页Computer Engineering

基　　金：国家自然科学基金资助项目(50775027)

摘　　要：基于冗余容错思想,设计基于现场可编程门阵列的双CPU容错控制器。该容错控制器在故障情况下可通过回溯重载进行故障判定和系统性能恢复,控制器控制律在传感器失效时能进行自我重构。仿真结果表明,该容错控制器通过冗余CPU的切换和控制律的重构实现了系统故障情况下的容错纠错功能。Based on the idea of redundant fault-tolerance,this paper designs a dual CPU fault-tolerant controller based on Field Programmable Gate Array（FPGA）. It can detect faults and resume system performance through checkpoint reload in case of failure,and control law can self-reconfigure when sensor faults occur in the system. Simulation results show that fault-tolerance and fault rectification functions can be achieved by switching the redundant CPU and reconfiguring the control law in case of system failure.

关 键 词：容错 重构 现场可编程门阵列 

分 类 号：TP302.8[自动化与计算机技术—计算机系统结构]