YHFT-DX高性能DSP中Cache失效流水设计  

Design of Cache Miss Pipelining in YHFT-DX High Performance DSP

作　　者：郭阳[1] 傅祎晖[1] 刘胜[1] 李勇[1] 

机构地区：[1]国防科技大学计算机学院,湖南长沙410073

出　　处：《国防科技大学学报》2009年第6期6-11,共6页Journal of National University of Defense Technology

基　　金：国家自然科学基金资助项目(60573173);新世纪优秀人才计划项目(NCET);教育部"高性能微处理器技术"创新团队资助项目(IRT0614)

摘　　要：YHFT-DX是国防科技大学自主研制的一款高性能DSP。以提升YHFT-DX的Cache性能为目标,研究了降低Cache失效延迟的优化策略,设计并实现了一种针对高频高性能DSP的一级数据Cache优化策略——失效流水。与传统优化策略相比,该策略将连续访问Cache的失效请求并进行流水化处理,使多个Cache失效延迟重叠,从而达到降低平均Cache失效代价的目的。将该策略应用到YHFT-DX芯片的一级数据Cache控制器的设计与优化中,使访问Cache失效引起的流水线停顿从8拍降为2拍,显著提升了系统性能。YHFT-DX is a high performance DSP designed by national university of defense technology. This paper focuses on improving Cache performance, investigates optimization methods to reduce Cache miss stall penalties, designs and implements an optimization method focusing on one level data Cache controller in high frequency and high performance DSP-miss pipelining. Compared with traditional optimization methods, this method can deal with continual cache misses in pipeline, which overlaps multi Cache miss stalls, and then it can achieve the goal of reducing Cache miss stall penalties. Applying the method to the design and optimization in one level data Cache controller in YHFT-DX DSP, the Cache miss stall is reduced from 8 cycles to 2 cycles, and the system performance is evidently improved.

关 键 词：DSP 失效流水 非阻塞Cache 数据预取 

分 类 号：TP368.1[自动化与计算机技术—计算机系统结构]