嵌入式软硬件低功耗优化研究综述  

Survey on power optimization of embedded software and hardware

作　　者：周宽久[1] 迟宗正[1] 西方[1] 

机构地区：[1]大连理工大学软件学院,辽宁大连116620

出　　处：《计算机应用研究》2010年第2期423-428,共6页Application Research of Computers

基　　金：大连市信息产业局IT专项基金资助项目(DL20080243)

摘　　要：随着时代的进步,制约着嵌入式设备广泛应用的障碍不再是处理器的速度、芯片的工艺,而是设备功耗。如何在相同能量的供给情况下工作时间最长、完成的任务最多,或者是运行相同的程序使用较少的能量成为嵌入式领域备受关注的研究方向。从硬件级、指令级和编译过程三个层次,由各层次相应公式的各个参数展开,对国内外的功耗优化研究现状进行综述和评价,并最终结合实验室SPARC仿真项目,提出基于SPARC仿真功耗优化研究的三个方向。With the development of the embedded technology, wide applications of embedded technology will not be restricted by the speed of the processor and the design of the chip, but by the power consumption. How to accomplish more tasks with the same hardware resources attracts more and more attentions from the domestic and abroad scientists. This paper reviewed three research directions from hardware level, instructions level and compiling level. It proposed three future research directions based on the SPARC simulation project.

关 键 词：功耗优化 硬件级 指令级 编译优化 静态功耗 漏电流 内联优化 高速暂存区 

分 类 号：TP368.1[自动化与计算机技术—计算机系统结构]