具有邻域子空间电路模块的低功耗测试设计  

Design for low power test of circuit modules with contiguous subspace

作　　者：肖继学[1] 谢永乐[2] 陈光[2] 胡兵[1] 

机构地区：[1]西华大学机械工程与自动化学院,成都610039 [2]电子科技大学自动化工程学院,成都610054

出　　处：《仪器仪表学报》2010年第1期137-142,共6页Chinese Journal of Scientific Instrument

基　　金：国家自然科学基金(90407007);西华大学人才培养/引进基金(R0820207);四川省科技厅应用基础(05JY029-137);西华大学重点科研基金(2G0720901)资助项目

摘　　要：本论文提出了具有邻域子空间电路模块的基于累加器测试的低功耗测试方法。该方法将测试矢量进行伪格雷码编码以降低电路的开关活动率,从而减少测试功耗。FPGA实现的由3～2计数器构成的8位行波进位加法器的实验表明,该方法降低了约17%的测试动态功耗。接着研究了该低功耗测试的硬件实现。通过复用电路中的加法器,巧妙、成功地避免了额外逻辑异或功能模块的引入。该设计将测试的额外硬件开销降至最低且不需要电路结构的调整。该低功耗测试方法能测试出邻域子空间对应电路基本组建模块内的任意固定性组合失效,且不会降低原电路的性能。For accumulator-based test of circuit modules with contiguous subspace, a low power test approach is proposed in this paper. With the approach, original test patterns are encoded in pseudo Gray code presentation to reduce the switching activity of the modules, and the decrease of test power consumption is resulted in. Results of the experiments based on FPGA show that the test approach reduces the dynamic power consumption by an average of about 17% for 8-bit ripple carry adder consisting of 3-2 counters. Then implementation of the low power test in hardware is exploited. Through reusing the adder in the circuit, introducing of additional XOR function modules is avoided skillfully and successfully. The design minimizes additional hardware overhead for the test and does not need adjusting the circuit structure. The low power test approach can detect any combinational stuck-at fault within the basic building cell of the modules corresponding to contiguous subspace without any degradation of original circuit performance.

关 键 词：低功耗 设计 测试生成器 

分 类 号：TP31[自动化与计算机技术—计算机软件与理论] TN7[自动化与计算机技术—计算机科学与技术]