多端口存储器控制器IP核的研究  

Research on the multiport memory controller IP core

作　　者：马秦生[1] 曹阳[1,2] 杨珺[1] 张宁[1] 

机构地区：[1]武汉大学电子信息学院,湖北武汉430079 [2]武汉大学软件工程国家重点实验室,湖北武汉430072

出　　处：《西安电子科技大学学报》2010年第1期142-147,共6页Journal of Xidian University

基　　金：国家863重大专项资助项目(2002AA1Z1490);教育部博士点基金资助项目(20040486049);华为技术有限公司高校合作研究基金资助项目

摘　　要：为了提高SoC系统中主设备访问外部存储器的访问带宽,设计了基于AHB总线的多端口存储器控制器IP核,并提出了基于提前仲裁和请求等待优先的仲裁策略.IP核中的多个主设备通过多个端口请求访问外部存储器,仲裁器在当前总线读/写操作完成前的提前仲裁时刻裁决出具有最高优先访问权的端口并对访问请求未获允许的端口设置请求等待时间,当提前仲裁时刻再次到达时,优先裁决等待时间到的端口.仿真和硬件验证结果表明,IP核的存储器访问带宽约为532 MB/s,最高总线利用率约为90%.In order to improve the memory bandwidth for masters accessing external memory in the SoC system, a multi-port memory controller IP core based on the AHB bus is developed. Also, an arbitration strategy for the early arbitration and request waiting priority is proposed. A number of masters in this IP core are requested to access the external memory through a number of ports. The arbitration selects the highestpriority port in the early arbitration moment and sets the request waiting time for the other ports that are not allowed the access request . The early arbitration moment occurs before the completion for the current read/ write operations. When the next early arbitration moment happens, the arbitration arbitrates these timeout ports in preference. The results of simulation and hardware verification indicate that the maximum memory bandwidth is about 532 MB/s and that the maximum bus utilization rate is about 90%.

关 键 词：专用集成电路 IP 逻辑设计 控制设备 存储设备 可重用性 多端口 仲裁器 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]