基于多级信道化的超宽带搜索接收机设计与实现  

Design and Implementation of Ultra-Wideband Reconnaissance Receiver Based on Multistage Channelized Processing

作　　者：王永明[1,2] 张尔扬[1] 王世练[1] 李长龙[3] 

机构地区：[1]国防科技大学电子科学与工程学院 [2]中国人民解放军94973部队 [3]中国人民解放军94865部队

出　　处：《信号处理》2010年第1期121-126,共6页Journal of Signal Processing

摘　　要：针对大瞬时带宽和高频率分辨率的实时侦察需求,联合采用模拟信道化和数字信道化技术完成了超宽带信号搜索接收机的设计与实现,并重点讨论了数字信道化接收机的高速FPGA数字系统设计。数字设计中,充分考虑了高速数据的可靠接收以及片内数字处理速度和资源的优化配置,确保系统良好的性能。实现和测试结果表明接收机性能稳定,能够完成大瞬时带宽内的无线电信号搜索任务。Considering the real-time reconnaissance requirement of large instantaneous bandwidth and high frequency resolution, the design and implementation of an ultra wideband reconnaissance receiver is accomplished based on both analog and digital channelized technologies. The high speed FPGA design for digital channelizcd receiver is specially discussed. Reliable receiving of high speed data as well as the processing speed and resource optimizing inside the chip are sufficiently considered to insure the good performance of the digital system. Implementation and test results verify the stability of the receiver and its ability to fulfill the radio recunnaissance in large instantaneous bandwidth.

关 键 词：无线电侦察 信道化接收机 测频 参数估计 FPGA实现 

分 类 号：TN971[电子电信—信号与信息处理]