基于块数字滤波器的高阶两通道时间交织∑Δ调制器的系统优化设计  

System Optimization Design of High-Order Two-Channel Time-Interleaved ∑Δ Modulator Based on Digital Block Filter

作　　者：凌朝东[1] 杨骁[1] 蔡灿辉[1] 

机构地区：[1]华侨大学信息科学与工程学院,福建厦门361021

出　　处：《信号处理》2010年第2期272-276,共5页Journal of Signal Processing

基　　金：国家自然科学基金项目(60772164)

摘　　要：时间交织技术是一种提高∑Δ调制器采样频率的有效方法,但是时间交织∑Δ调制器对通道之间的失配非常敏感。在传统噪声传递函数(NTF)中增加一个z=-1的零点,可以减小折叠到信号带宽内的噪声。在已提出的基于块数字滤波器的二阶两通道时间交织∑Δ调制器结构的基础上,提出了一种高阶两通道时间交织∑Δ调制器的系统优化设计方法,该方法对系统的稳定性、噪声传递函数零极点的优化进行了考虑。采用该方法,设计了一种带宽为4MHz应用于数字视频广播系统中的高阶两通道时间交织调制器的系统结构。仿真结果表明,该调制器具有较大的稳定输入范围以及对通道失配不敏感的特点。Time-interleaving is an efficient approach to increase the sampling rate of ∑Δ modulators,but time-interleaved（TI） ∑Δ modulators are sensitive to channel mismatch.Recently,a solution for this problem has been proposed with a zero of z=-1 and its corresponding pole in the noise transfer function.Based on the proposed second-order two-channel TI modulator,an approach of system optimization design is presented for high-order two-channel TI modulators.The system stability and optimization of zeros/poles are considered.As an example,a system of high-order two-channel TI ∑Δ modulator is designed with bandwidth of 4 MHz,which is suitable for application of digital video broadcasting-terrestrial （DVB-T）.Simulation results show that the proposed ∑Δ modulator has a large input signal range and is insensitive to channel mismatch.

关 键 词：∑Δ调制器 折叠噪声 高阶 时间交织 块数字滤波器 

分 类 号：TN43[电子电信—微电子学与固体电子学]